1. Field of the Invention
This invention is a system and set of circuits for regenerating a clock signal in response to random antipodal data, i.e., data having two voltage levels, over an arbitrarily wide range of bit rates. It has applicability in digital communications receivers.
2. Description of the Prior Art
U.S. Pat. No. 4,210,776 to VanMeter is a linear digital phase lock loop which cannot acquire or even operate significantly beyond the loop bandwidth, unlike the present invention which can acquire and operate throughout an arbitrarily wide frequency range. (Usually, the loop bandwidth is no more than 5% of the data rate because of noise considerations.) VanMeter is, however, a second order loop using a five bit adder, as in the present invention. VanMeter's circuit is entirely digital, e.g., he uses a digital frequency integrator, whereas the present invention contains analog circuitry, and thus is capable of a wider frequency operating range and more precise phase and frequency alignment. VanMeter does not state his circuit to be synchronous; the present invention operates synchronously.
U.S. Pat. No. 4,122,405 to Tietz is a PLL lock indicator. Tietz's pulse width discriminator 14 can work only at a fixed frequency because it has fixed values of R and C. His phase comparator 10 operates only for periodic not random data, whereas the present invention is operable for random data.
U.S. Pat. No. 3,646,452 to Horowitz is a PLL for self clocking data, i.e., there are at most three consecutive bits without a transition. On the other hand, the present invention operates on random data. Horowitz is suitable for magnetic recording, not for communications receivers as in the present invention.
Bellisio, "A New Phase-locked Timing Recovery Method for Digital Regenerators", IEEE 1976 Communications Conference proceedings, page 10-17 et seq., is a second order PLL which can operate and acquire over only a .+-.20% data rate range. Bellisio's approach is analog. On the other hand, the combination of digital circuits, frequency sweep, and lock decision gives the present invention an arbitrarily wide frequency range. The present invention uses a binary counter for a phase detector, which is not present in Bellisio. Bellisio does not have the present invention's capability of determining when lock has occurred.
U.S. patent application Ser. No. 050,566, filed June 21, 1979, and commonly assigned with the present invention, is a second order phase lock loop. However, there is no provision for acquisition significantly beyond the loop bandwidth. Furthermore, this patent application does not provide for lock decisions as in the present invention.
U.S. Pat. No. 4,031,317 to McClain is a PLL intended for a single frequency. It tracks just phase, not frequency.
U.S. Pat. No. 3,781,695 to Jackson is a digital PLL which operates on periodic inputs only, not on random data.
U.S. Pat. No. 3,959,601 to Olevsky is a bit synchronizer which does not have any provision for acquisition. The circuit is very complex and expensive since it includes a frequency synthesizer, up and down converters, a 30 MHz bandpass filter, a variable time delay, etc. The data rate must be accurately programmed beforehand before the synchronizer can be operated. After the frequency has been programmed, frequency synthesizer tracking occurs in the vicinity of the loop bandwidth only.
U.S. Pat. No. 4,019,153 to Cox is a first order PLL which operates on periodic inputs only.
All of the PLL circuits outlined above excepting Bellisio are intended to be used at a single data rate or at a countably finite number of data rates. They are not capable of multiple rate operation unless they are provided with several master oscillators or with a frequency synthesizer. Use of several oscillators is expensive and bulky. Even use of a frequency synthesizer requires that the data rate be known with good accuracy or requires careful manual or computer tuning.
The hybrid phase lock loop of the present invention is designed to operate at any data rate. The circuit is designed to rapidly acquire lock. The operator selects the appropriate half octave for the received data rate. Alternatively, an autorange capability is provided to step the frequency by half octaves if the data rate is totally unknown. The circuitry for the range of 3.75 Kbps to 480 Kbps has been built on a single 6".times.17" circuit board and is relatively inexpensive.
None of the above circuits provides a capability for deciding when lock has been acquired, and an indication of same, as in the present invention.